CDC 6000 CPU Instruction Set

This table lists the CPU instructions of a Control Data Corporation 6000 Series computer. It does not list CMU (Compare-and-Move Unit) instructions that briefly appeared on the later Cyber 70 Series. All instructions are either 15 or 30 bits long, and are written in traditional octal.

Instructions which, from my observation, were rarely used are in red. Instructions that were particularly frequently used are in blue.

Octal Mnemonic Description 6500
00000 PS Program Stop Infinite
01xxkkkkkk RJ K Return Jump (call subroutine) 21
011jK RE Bj+K Read ECS from X0 to A0 for Bj+K words ?
012jK WE Bj+K Write ECS from A0 to X0 for Bj+K words ?
013jK XJ Bj+K Exchange jump (context switch) ?
02ixkkkkkk JP Bi+K Jump 5/13
030jkkkkkk ZR Xj,K Jump if zero 5/13
031jkkkkkk NZ Xj,K Jump if non-zero 5/13
032jkkkkkk PL Xj,K Jump if positive 5/13
033jkkkkkk NG Xj,K Jump if negative 5/13
034jkkkkkk IR Xj,K Jump if In Range (not floating point infinity) 5/13
035jkkkkkk OR Xj,K Jump if Out of Range (floating point infinity) 5/13
036jkkkkkk DF Xj,K Jump if Definite (good floating point value) 5/13
037jkkkkkk ID Xj,K Jump if InDefinite (bad floating point value) 5/13
04ijkkkkkk EQ Bi,Bj,K Jump if Bi=Bj (if i=j, unconditional jump) 5/13
05ijkkkkkk NE Bi,Bj,K Jump if Bi<>Bj 5/13
06ijkkkkkk GE Bi,Bj,K Jump if Bi>Bj 5/13
07ijkkkkkk LT Bi,Bj,K Jump if Bi<=Bj 5/13
10ijx BXi Xj Move Xj to Xi 5
11ijk BXi Xj*Xk Xi:=Xj AND Xk 5
12ijk BXi Xj+Xk Xi:=Xj OR Xk 5
13ijk BXi Xj-Xk Xi:=Xj XOR Xk (often used to zero an X reg) 5
14ixk BXi -Xk Xi:=NOT Xk 5
15ijk BXi -Xj*Xk Xi:=(NOT Xj) AND Xk 5
16ijk BXi -Xj+Xk Xi:=(NOT Xj) OR Xk 5
17ijk BXi -Xj-Xk Xi:=(NOT Xj) XOR Xk 5
20ivv LXi vv Left shift Xi vv bits circular 6
21ivv AXi vv Right shift Xi vv bits w/ sign extend 6
22ijk LXi Bj,Xk Xi:=Xk left shifted circular Bj bits 6
23ijk AXi Bj,Xk Xi:=Xk right shifted w/ sign extend Bj bits 6
24ijk NXi Bj,Xk Xi:=Xk normalized; Bj:=# bits Xk was shifted 6
25ijk ZXi Bj,Xk Xi:=Xk normalized w/ round; Bj:=# bits Xk was shifted 6
26ijk UXi Bj,Xk Xi:=Mantissa of Xk; Bj:=exponent 6
27ijk PXi Bj,Xk Xi:=Xk with exponent Bj 6
30ijk FXi Xj+Xk Xi:=Xj+Xk (floating point) 11
31ijk FXi Xj-Xk Xi:=Xj-Xk (floating point) 11
32ijk DXi Xj+Xk Xi:=Xj+Xk (bottom word, double prec.) 11
33ijk DXi Xj-Xk Xi:=Xj-Xk (bottom word, double prec.) 11
34ijk RXi Xj+Xk Xi:=Xj+Xk (rounded floating point) 11
35ijk RXi Xj-Xk Xi:=Xj-Xk (rounded floating point) 11
36ijk IXi Xj+Xk Xi:=Xj+Xk (60-bit integer) 6
37ijk IXi Xj-Xk Xi:=Xj-Xk (60-bit integer) 6
40ijk FXi Xj*Xk Xi:=Xj*Xk (floating point) 57
41ijk RXi Xj*Xk Xi:=Xj*Xk (rounded floating point) 57
42ijk DXi Xj*Xk Xi:=Xj*Xk (bottom word, double prec., or 48-bit integer) 57
43ivv MXi vv Xi:=Mask of vv bits at top of word 6
44ijk FXi Xj/Xk Xi:=Xj/Xk (floating point) 57
45ijk RXi Xj/Xk Xi:=Xj/Xk (rounded floating point) 57
46000 NO No operation 3
47ixk CXi Xk Xi:=# of bits in Xk (population count) 68
50ijkkkkkk SAi Aj+K Ai:=Aj+K 6/12/10
51ijkkkkkk SAi Bj+K Ai:=Bj+K 6/12/10
52ijkkkkkk SAi Xj+K Ai:=Xj+K 6/12/10
53ijk SAi Xj+Bk Ai:=Xj+Bk 6/12/10
54ijk SAi Aj+Bk Ai:=Aj+Bk 6/12/10
55ijk SAi Aj-Bk Ai:=Aj-Bk 6/12/10
56ijk SAi Bj+Bk Ai:=Bj+Bk 6/12/10
57ijk SAi Bj-Bk Ai:=Bj-Bk 6/12/10
60ijkkkkkk SBi Aj+K Bi:=Aj+K 5
61ijkkkkkk SBi Bj+K Bi:=Bj+K (SB0 B0+46000 was a common 30-bit noop) 5
62ijkkkkkk SBi Xj+K Bi:=Xj+K 5
63ijk SBi Xj+Bk Bi:=Xj+Bk 5
64ijk SBi Aj+Bk Bi:=Aj+Bk 5
65ijk SBi Aj-Bk Bi:=Aj-Bk 5
66ijk SBi Bj+Bk Bi:=Bj+Bk 5
67ijk SBi Bj-Bk Bi:=Bj-Bk 5
70ijkkkkkk SXi Aj+K Xi:=Aj+K (18-bit with sign extend) 6
71ijkkkkkk SXi Bj+K Xi:=Bj+K (18-bit with sign extend) 6
72ijkkkkkk SXi Xj+K Xi:=Xj+K (18-bit with sign extend) 6
73ijk SXi Xj+Bk Xi:=Xj+Bk (18-bit with sign extend) 6
74ijk SXi Aj+Bk Xi:=Aj+Bk (18-bit with sign extend) 6
75ijk SXi Aj-Bk Xi:=Aj-Bk (18-bit with sign extend) 6
76ijk SXi Bj+Bk Xi:=Bj+Bk (18-bit with sign extend) 6
77ijk SXi Bj-Bk Xi:=Bj-Bk (18-bit with sign extend) 6

Lower-case letters are octal digits, as follows:

x = Don't care
i = Register number
j = Register number
k = Register number if single digit, else part of 18-bit constant (usually used as a CPU memory address)
vv = 6-bit constant

Uppercase K = 18-bit CPU memory address

The 6500 Cycles column describes the speed of the instruction on a CDC 6500. Cycle times are minor cycles, with one minor cycle being 100ns.

Cycle times marked as A/B mean the instruction took A cycles if the condition was false, and B if true. Cycle times marked as A/B/C mean the instruction took A cycles if i=0, B cycles if i=1-5, and C cycles if i=6 or 7.

Adapted from Ralph Grishman's Assembly Language Programming for the Control Data 6000 Series and the Cyber 70 Series. (Don't make the mistake, as I sometimes did, of confusing Ralph Grishman with Ralph Griswold, the creator of the SNOBOL and Icon programming languages.)  Portions from 6000 COMPASS Version 2 Reference Manual, CDC publication number 60279900.

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